比如流水线分为F D E M W，
branch logic 放在D，包括取出imm和regidx。
计算放在E，计算出的target address直接回馈给F或者BF。
这样做其实是在F阶段不知道branch结果的时候默认取值pc+4。当branch指令走到E阶段时，这时下一条指令已经走到了D，这条正是delay slot instruction。
所以如果指令集里是带delay slot，比如mips和sparc这样，branch taken的时候不需要刷前面的流水线，直接改变F阶段的pc。（要是有BF阶段，可能还不一样）
看chiplab时，gs232c_front()里给下一阶段的信号是3个port，每个port大概是这些信号：
.o_allow (de2_accept ),
.o_valid ({de1_port2_valid,de1_port1_valid,de1_port0_valid}),
.o_port0_pc (de1_port0_pc ),// O, 32
.o_port0_inst (de1_port0_inst ),// O, 32
.o_port0_taken (de1_port0_br_taken ),// O, 1
.o_port0_target (de1_port0_br_target),// O, 30
.o_port0_ex (de1_port0_exception),// O, 1
.o_port0_exccode (de1_port0_exccode ),// O, 5
.o_port0_hint (de1_port0_hint ),
.o_port1_pc (de1_port1_pc ),// O, 32
.o_port1_inst (de1_port1_inst ),// O, 32
.o_port1_taken (de1_port1_br_taken ),// O, 1
.o_port1_target (de1_port1_br_target),// O, 30
.o_port1_ex (de1_port1_exception),// O, 1
.o_port1_exccode (de1_port1_exccode ),// O, 5
.o_port1_hint (de1_port1_hint ),
.o_port2_pc (de1_port2_pc ),// O, 32
.o_port2_inst (de1_port2_inst ),// O, 32
.o_port2_taken (de1_port2_br_taken ),// O, 1
.o_port2_target (de1_port2_br_target),// O, 30
.o_port2_ex (de1_port2_exception),// O, 1
.o_port2_exccode (de1_port2_exccode ),// O, 5
.o_port2_hint (de1_port2_hint ),
没有刷D阶段流水线的信号，基本是取值后直接就发给后面的逻辑处理了，最多同时发出三条指令。o_valid[3]表示哪个port valid。
而LoongArch是没有delay slot的， 这里搞了半天一直在找刷流水线的信号。
因为br_cancel 1是表示branch taken（名字好像正好反了。。），br_target是目标地址。这俩信号是从后面回送给F阶段的。这段代码在gs232c_front()->gs232c_pipe_pc()里。
assign pc_next = wb_cancel ? wb_target :
br_cancel ? br_target :
pr_cancel ? pr_target :
bt_cancel ? bt_target : {pc_seq,2'h0};
感觉这怎么可能不刷流水线就能这么发出去指令就不管了呢。
后来想在opensparc t1看看怎么刷流水线的。结果还没找到。原来sparc也带delay instruction，比mips规则更复杂点，还带个anull bit。
The instruction following a delayed control-transfer instruction is called a
delay instruction. Setting the annul bit in a conditional delayed control-
transfer instruction causes the delay instruction to be annulled (that is, to have no effect) if and only if the branch is not taken. Setting the annul bit in an
unconditional delayed control-transfer instruction (“branch always”) causes
the delay instruction to be always annulled.
在tlu（trap logic unit）在得到中断或异常的时候刷后面整条的流水线，但还没仔细看这部分。
要想看annulled bit怎么工作的，可以追anull_next_e
题外话，看到了这么个bug fix
//bug6838,bug6989 - interrupt issued in annulled delay slot resets wm_other mask in e-stage; this
// reset causes switch logic to lose a long latency op(div) which set the wm_other mask
// in s-stage. Note that the div is issued to FPU. the ifu re-issues the interrupt -
// which results in flush. this kills the long latency op and div is lost
//
// fix is to detect interrupt in anulled delay slot followed by long latency op and
// not reset the wm_other mask.
//
// 10/07/04 - fix changed to delay setting of wm_other mask from d-cycle to e-cycle. hence
// removing the kill in killed_inst_done_e
//
// assign killed_inst_done_e = (fcl_dtu_inst_vld_e & swc_e | //sw inst
// fcl_dtu_intr_vld_e) & // any intr
// dtu_inst_anull_e;
那chiplab这个是怎么回事呢，结果是这个cpu并不是一个周期一条指令，具体说是我在看wave的时候是12个clock o_port0_pc走一条指令。不知道是不是配置的关系。
