I want to trace how the "add" instruction goes through the ex1 and ex2 stages. Because there are several things that I feel weird about. For one, there are ALUs in both ex1 and ex2. And for simple arithmetic operations such as add, it only takes one cycle to finish.
I traced ex1_port0_a, ex1_port0_b, ex1_port0_op, ex1_port0_double, ex1_port0_c, ex1_port0_ignore_a, ex1_port0_ignore_b, ex1_port0_b_get_a. They come from the issue stage and go to ex1. They are calculated in the ALU and get the result ex1_alu0_res, but the result returns to the issue stage. I guess this is for the forwarding-related stuff. Then, the ex1 stage passes those signals to the ex2 stage as ex2_port0_a, ex2_port0_b, etc.
I guess it will be calculated again. I get confused because the ALU is not a tiny functional unit.
Let's see the forwarding-related code in the ex1_stage.
737 ////forwarding related
738 //forwarding check
739 assign r1_1_w1_fw = ex2_port0_valid && (ex1_raddr0_0 == ex2_port0_rf_target) && (ex2_port0_rf_target != 5'd0);
740 assign r1_2_w1_fw = ex2_port0_valid && (ex1_raddr0_1 == ex2_port0_rf_target) && (ex2_port0_rf_target != 5'd0);
741 assign r1_1_w2_fw = ex2_port1_valid && (ex1_raddr0_0 == ex2_port1_rf_target) && (ex2_port1_rf_target != 5'd0);
742 assign r1_2_w2_fw = ex2_port1_valid && (ex1_raddr0_1 == ex2_port1_rf_target) && (ex2_port1_rf_target != 5'd0);
First of all, the naming is inconsistent.
r1_1_w1_fw means the reading of rf (raddr0_0) is conflicted with the writing of rf in the next cycle (ex2). This signal should be named r0_0_w1_fw.
后面再跟ex2_port0_a，
在issue模块的参数里，
1255 //forwarding related 1256 .ex1_raddr0_0 (ex1_raddr0_0 ), 1257 .ex1_raddr0_1 (ex1_raddr0_1 ), 1258 .ex1_raddr1_0 (ex1_raddr1_0 ), 1259 .ex1_raddr1_1 (ex1_raddr1_1 ), 1260 .ex1_raddr2_0 (ex1_raddr2_0 ), 1261 .ex1_raddr2_1 (ex1_raddr2_1 ), 1262 1263 .ex1_alu0_res (ex1_alu0_res ), 1264 .ex1_alu1_res (ex1_alu1_res ), 1265 .ex1_bru_res (bru_link_pc ), 1266 .ex1_none0_res (ex1_none0_result ), 1267 .ex1_none1_res (ex1_none1_result ), 1268 1269 .ex2_port0_src (ex2_port0_src ), 1270 .ex2_port0_valid (ex2_port0_valid ), 1271 .ex2_port0_rf_target (ex2_port0_rf_target), 1272 .ex2_port1_src (ex2_port1_src ), 1273 .ex2_port1_valid (ex2_port1_valid ), 1274 .ex2_port1_rf_target (ex2_port1_rf_target), 1275 1276 .ex2_alu0_res (ex2_alu0_res ), 1277 .ex2_alu1_res (ex2_alu1_res ), 1278 .ex2_lsu_res (ex2_lsu_res ), 1279 .ex2_bru_res (ex2_bru_link_pc ), 1280 .ex2_none0_res (ex2_none0_result ), 1281 .ex2_none1_res (ex2_none1_result ), 1282 .ex2_mul_res (ex2_mul_res ), 1283 .ex2_div_res (ex2_div_res ) 1284 );
能看到ex1_port0_res ，ex2_port0_res，两个ex stage里的alu的结果都送回issue里用来forwarding了，这里肯定得有点问题。
